The problem the invention solves concerns the adjustment of a delay function for digital data transmission. This delay function usually is realized with the help of a serial shift register or an addressable RAM, or alternatively using a standalone elastic store register, combined with a PLL and a VCO.
In solutions known in the art, which use serial shift registers the input or output of a serial shift register was adjusted when changing the delay, i.e. it virtually was moved with the help of a multiplexer. A disadvantage of this solution is that one data element either is repeated or respectively is left out (depending on whether the delay has to be increased or decreased).
In prior art solutions, which use an addressable RAM the adjustment of a delay function was implemented by changing the dynamic addressing of the write or read pointers, i.e. the address difference is either increased or decreased. Disadvantage of this solution is exactly the same as in solutions using serial shift registers described above.
In solutions using a standalone elastic store register combined with a PLL and a VCO it is possible to make a phase offset in order to get an adjustment of delay function. Disadvantage of this solution is that it is difficult to make the elastic store register big enough, because the PLL's phase detector constant (Volts/radiants) decreases and it may be difficult to vary the phase by adding a DC voltage to the control circuit (in case of an analogue PLL) or adding an offset (in case of a digital PLL, i.e. when the PLL's behaviour is realized by numeric operations instead of discrete components).
Hence, an improved apparatus and method for adjustment of a digital delay function of a data memory would be advantageous and in particular one that allows to adjust the digital delay function without distorting the data information.